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Show HN: Write, simulate and synthesize VHDL/Verilog in the browser

HN #49,023,076 | submitted 2026-07-23 15:22 UTC | risingedge.pro

39 observationsby wozniakpawel
1 points
Latest score
1 comments
Latest comments
0
Score change

Rank history is not tracked yet in the current dataset, so this first slice focuses on score and comment movement.

Score

Range 1 to 1
2026-07-23 15:30 UTC2026-07-23 18:31 UTC

Comments

Range 0 to 1
2026-07-23 15:30 UTC2026-07-23 18:31 UTC

Observation history

Observation times are irregular and reflect when the tracker refreshed this story.

First 2026-07-23 15:30 UTCLatest 2026-07-23 18:31 UTC
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2026-07-23 15:30 UTC10not tracked